1. Field of the Invention
The present invention relates generally to dual damascene semiconductor manufacturing processes, and more particularly, to methods and systems for planarizing features and layers in a semiconductor manufacturing process.
2. Description of the Related Art
Dual damascene manufacturing processes are becoming more common in semiconductor manufacturing. In a typical dual damascene manufacturing process, one or more conductive materials are deposited in previously patterned trenches and vias formed in a semiconductor substrate or films formed on the semiconductor substrate to form the desired electrical circuit interconnects. An excess or overburden portion of the conductive material is often formed. The overburden portion of the conductive material is unnecessary and undesirable and must be removed both to produce a damascene feature and to provide a planar surface for subsequent processing.
The overburden portion of the conductive material is typically removed from the semiconductor substrate through chemical mechanical polishing (CMP) and electro-chemical polishing (ECP) (e.g., etching) processes and combinations of CMP and ECP processes. Each of these processes has significant shortfalls. By way of example, ECP typically has a relatively low throughput, poor uniformity and inability to effectively remove non-conductive material.
CMP requires physical contact processes which typically leave conductive residues, or cause corrosion of the various materials, or result in non-uniform removal, and the inability to suitably planarize interconnect and interlevel dielectric (ILD) top surface. CMP can also cause stress related damage (e.g., interlayer delamination, peeling) to remaining interconnect and ILD structures. The CMP-caused stress damage is further exacerbated by the very poor inter-layer adhesion characteristics of the more-recently used materials. Reducing the physical force of the CMP process to reduce the physical stress can often result in unacceptably low throughput rates and other poor process performance parameters.
In view of the foregoing, there is a need for an improved planarizing system and method to uniformly and substantially remove overburden material while minimizing physical stress to the remaining features. The improved planarizing system and method should be suitable for use in semiconductor manufacturing and should be applicable to processes such as a dual damascene process or other semiconductor manufacturing processes.
Broadly speaking, the present invention fills these needs by providing a system and method for planarizing a semiconductor substrate. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, computer readable media, or a device. Several inventive embodiments of the present invention are described below.
One embodiment includes a method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer. The conductive interconnect material can include copper, copper containing conductive materials and elemental copper and other conductive material. The pattern can be formed on the patterned semiconductor substrate in a dual damascene process.
Planarizing the additional layer and the overburden portion can include substantially eliminating a local, pattern dependant non-uniformity. Planarizing the additional layer and the overburden portion can also include substantially eliminating a local, pattern dependant non-uniformity without imparting mechanical stress to the plurality of features.
The additional layer and the overburden portion can have a substantially 1:1 etch selectivity. The additional layer is formed substantially planar. The additional layer is a substantially planar fill material. Planarizing the additional layer and the overburden portion can also include etching the additional layer and at least part of the overburden portion. A second etch process to expose a barrier layer formed on the patterned features can also be included.
Forming the additional layer on the overburden portion can include chemically converting a top surface and a top portion of the overburden portion. Chemically converting a top surface and a top portion of the overburden portion can include exposing the top surface of the overburden portion to a reactant gas such as a halogen. The additional layer is a halide reactant product of the overburden portion.
Planarizing the additional layer and the overburden portion can include etching the additional layer and at least part of the overburden portion. Planarizing the additional layer and the overburden portion can also include a reiterative process that includes etching the additional layer, forming a second additional layer, and etching the second additional layer. The reiterative process can be an in situ reiterative process.
In another embodiment, a semiconductor device is formed by a method including receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple features in the pattern. The conductive interconnect material having an overburden portion that includes a localized non-uniformity. An additional layer is formed on the overburden portion and the additional layer and the overburden portion are planarized. The additional layer being substantially entirely removed in the planarizing process.
Yet another embodiment includes a method of forming a dual damascene interconnect structure that includes receiving a dual damascene patterned semiconductor substrate. The dual damascene patterned semiconductor substrate having a conductive interconnect material filling multiple features in the dual damascene pattern. The conductive interconnect material having an overburden portion that includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer being formed substantially planar. The additional layer and at least part of the overburden portion are etched to substantially planarize the overburden portion, the additional layer being substantially entirely removed.
Still another embodiment includes a method of forming a dual damascene interconnect structure that includes receiving a dual damascene patterned semiconductor substrate. The dual damascene patterned semiconductor substrate having a conductive interconnect material filling multiple features in the dual damascene pattern. The conductive interconnect material having an overburden portion that includes a localized non-uniformity. A top surface and a top portion of the overburden portion are chemically converted to form an additional layer on the overburden portion. The additional layer and the overburden portion are planarized, the additional layer being substantially entirely removed in the planarizing process. The planarizing process including a reiterative process that includes etching the additional layer, forming a second additional layer, and etching the second additional layer. The reiterative process can be continued until the remaining overburden portion is substantially planarized.
The present invention provides the advantage of minimizing mechanical stress while substantially eliminating localized non-uniformities.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.